Clustering the dominant defective patterns in semiconductor wafer maps

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dc.contributor.authorTaha, Kamal
dc.contributor.authorSalah, K
dc.contributor.authorYoo, P D
dc.date.accessioned2018-01-19T12:20:32Z
dc.date.available2018-01-19T12:20:32Z
dc.date.issued2017-10-30
dc.description.abstractIdentifying defect patterns on wafers is crucial for understanding the root causes and for attributing such patterns to specific steps in the fabrication process. We propose in this paper a system called DDPfinder that clusters the patterns of defective chips on wafers based on their spatial dependence across wafer maps. Such clustering enables the identification of the dominant defect patterns. DDPfinder clusters chip defects based on how dominant are their spatial patterns across all wafer maps. A chip defect is considered dominant, if: (1) it has a systematic defect pattern arising from a specific assignable cause, and (2) it displays spatial dependence across a larger number of wafer maps when compared with other defects. The spatial dependence of a chip defect is determined based on the contiguity ratio of the defect pattern across wafer maps. DDPfinder uses the dominant chip defects to serve as seeds for clustering the patterns of defective chips. This clustering procedure allows process engineers to prioritize their investigation of chip defects based on the dominance status of their clusters. It allows them to pay more attention to the ongoing manufacturing processes that caused the dominant defects. We evaluated the quality and performance of DDPfinder by comparing it experimentally with eight existing clustering models. Results showed marked improvement.en_UK
dc.identifier.citationTaha K, Salah K, Yoo P, Clustering the dominant defective patterns in semiconductor wafer maps, IEEE Transactions on Semiconductor Manufacturing, Vol. 31, Issue 1, February 2018, pp. 156-165en_UK
dc.identifier.issn0894-6507
dc.identifier.urihttp://doi.org/10.1109/TSM.2017.2768323
dc.identifier.urihttp://dspace.lib.cranfield.ac.uk/handle/1826/12910
dc.language.isoenen_UK
dc.publisherIEEEen_UK
dc.rightsAttribution-NonCommercial 4.0 International*
dc.rights©2017 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
dc.rights.urihttp://creativecommons.org/licenses/by-nc/4.0/*
dc.subjectClustering algorithymsen_UK
dc.subjectSemiconductor device modelingen_UK
dc.subjectSystematicsen_UK
dc.subjectPartitioning algorithmsen_UK
dc.subjectFabricationen_UK
dc.subjectManufacturing processesen_UK
dc.subjectIntegrated circuitsen_UK
dc.subjectClustering of defective chipsen_UK
dc.subjectWafer defect patternsen_UK
dc.subjectSpatial autocorrelationen_UK
dc.subjectWafer mapen_UK
dc.titleClustering the dominant defective patterns in semiconductor wafer mapsen_UK
dc.typeArticleen_UK

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