Clustering the dominant defective patterns in semiconductor wafer maps

Date

2017-10-30

Supervisor/s

Journal Title

Journal ISSN

Volume Title

Publisher

IEEE

Department

Type

Article

ISSN

0894-6507

Format

Free to read from

Citation

Taha K, Salah K, Yoo P, Clustering the dominant defective patterns in semiconductor wafer maps, IEEE Transactions on Semiconductor Manufacturing, Vol. 31, Issue 1, February 2018, pp. 156-165

Abstract

Identifying defect patterns on wafers is crucial for understanding the root causes and for attributing such patterns to specific steps in the fabrication process. We propose in this paper a system called DDPfinder that clusters the patterns of defective chips on wafers based on their spatial dependence across wafer maps. Such clustering enables the identification of the dominant defect patterns. DDPfinder clusters chip defects based on how dominant are their spatial patterns across all wafer maps. A chip defect is considered dominant, if: (1) it has a systematic defect pattern arising from a specific assignable cause, and (2) it displays spatial dependence across a larger number of wafer maps when compared with other defects. The spatial dependence of a chip defect is determined based on the contiguity ratio of the defect pattern across wafer maps. DDPfinder uses the dominant chip defects to serve as seeds for clustering the patterns of defective chips. This clustering procedure allows process engineers to prioritize their investigation of chip defects based on the dominance status of their clusters. It allows them to pay more attention to the ongoing manufacturing processes that caused the dominant defects. We evaluated the quality and performance of DDPfinder by comparing it experimentally with eight existing clustering models. Results showed marked improvement.

Description

Software Description

Software Language

Github

Keywords

Clustering algorithyms, Semiconductor device modeling, Systematics, Partitioning algorithms, Fabrication, Manufacturing processes, Integrated circuits, Clustering of defective chips, Wafer defect patterns, Spatial autocorrelation, Wafer map

DOI

Rights

Attribution-NonCommercial 4.0 International
©2017 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Relationships

Relationships

Supplements

Funder/s