Elshakhs, Yahia S.Deliparaschos, Kyriakos M.Charalambous, ThemistoklisOliva, GabrieleZolotas, Argyrios2024-03-192024-03-192024-01-15Elshakhs YS, Deliparaschos KM, Charalambous T, et al., (2024) A comprehensive survey on Delaunay Triangulation: applications, algorithms, and implementations over CPUs, GPUs, and FPGAs. IEEE Access. Volume 12, 2024, pp. 12562-125852169-3536https://doi.org/10.1109/ACCESS.2024.3354709https://dspace.lib.cranfield.ac.uk/handle/1826/21043Delaunay triangulation is an effective way to build a triangulation of a cloud of points, i.e., a partitioning of the points into simplices (triangles in 2D, tetrahedra in 3D, and so on), such that no two simplices overlap and every point in the set is a vertex of at least one simplex. Such a triangulation has been shown to have several interesting properties in terms of the structure of the simplices it constructs (e.g., maximising the minimum angle of the triangles in the bi-dimensional case) and has several critical applications in the contexts of computer graphics, computational geometry, mobile robotics or indoor localisation, to name a few application domains. This review paper revolves around three main pillars: (I) algorithms, (II) implementations over central processing units (CPUs), graphics processing units (GPUs), and field programmable gate arrays (FPGAs), and (III) applications. Specifically, the paper provides a comprehensive review of the main state-of-the-art algorithmic approaches to compute the Delaunay Triangulation. Subsequently, it delivers a critical review of implementations of Delaunay triangulation over CPUs, GPUs, and FPGAs. Finally, the paper covers a broad and multi-disciplinary range of possible applications of this technique.en-UKAttribution-NonCommercial-NoDerivatives 4.0 InternationalDelaunay triangulationapplications of Delaunay triangulationalgorithmic approaches to Delaunay triangulationCPU implementation of Delaunay triangulationGPU implementation of Delaunay triangulationFPGA implementation of Delaunay triangulationVoronoi diagramCPUGPUFPGAArticle