Design of hardware-orientated security towards trusted electronics.
| dc.contributor.advisor | Jennions, Ian K. | |
| dc.contributor.advisor | Samie, Mohammad | |
| dc.contributor.author | Randa, Maulana | |
| dc.date.accessioned | 2024-03-07T12:35:12Z | |
| dc.date.available | 2024-03-07T12:35:12Z | |
| dc.date.issued | 2020-07 | |
| dc.description.abstract | While the Internet of Things (IoT) becomes one of the critical components in the cyber-physical system of industry 4.0, its root of trust still lacks consideration. The purpose of this thesis was to increase the root of trust in electronic devices by enhance the reliability, testability, and security of the bottom layer of the IoT system, which is the Very Large-Scale Integration (VLSI) device. This was achieved by implement a new class of security primitive to secure the IJTAG network as an access point for testing and programming. The proposed security primitive expands the properties of a Physically Unclonable Function (PUF) to generate two different responses from a single challenge. The development of such feature was done using the ring counter circuit as the source of randomness of the PUF to increase the efficiency of the proposed PUF. The efficiency of the newly developed PUF was measured by comparing its properties with the properties of a legacy PUF. The randomness test done for the PUF shows that it has a limitation when implemented in sub-nm devices. However, when it was implemented in current 28nm silicon technology, it increases the sensitivity of the PUF as a sensor to detect malicious modification to the FPGA configuration file. Moreover, the efficiency of the developed bimodal PUF increases by 20.4% compared to the legacy PUF. This shows that the proposed security primitive proves to be more dependable and trustworthy than the previously proposed approach. | en_UK |
| dc.description.coursename | PhD in Transport Systems | en_UK |
| dc.description.notes | Samie, Mohammad (Associate) | |
| dc.identifier.uri | https://dspace.lib.cranfield.ac.uk/handle/1826/20945 | |
| dc.language.iso | en | en_UK |
| dc.publisher | Cranfield University | en_UK |
| dc.publisher.department | SAS | en_UK |
| dc.rights | © Cranfield University, 2020. All rights reserved. No part of this publication may be reproduced without the written permission of the copyright holder. | en_UK |
| dc.subject | hardware security | en_UK |
| dc.subject | physically unclonable function | en_UK |
| dc.subject | random number generator | en_UK |
| dc.subject | JTAG | en_UK |
| dc.subject | IJTAG | en_UK |
| dc.subject | FPGA | en_UK |
| dc.title | Design of hardware-orientated security towards trusted electronics. | en_UK |
| dc.type | Thesis or dissertation | en_UK |
| dc.type.qualificationlevel | Doctoral | en_UK |
| dc.type.qualificationname | PhD | en_UK |