Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation

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dc.contributor.authorAslam, Sohaib
dc.contributor.authorJennions, Ian K.
dc.contributor.authorSamie, Mohammad
dc.contributor.authorPerinpanayagam, Suresh
dc.contributor.authorFang, Yisen
dc.date.accessioned2020-03-06T16:45:25Z
dc.date.available2020-03-06T16:45:25Z
dc.date.issued2020-02-11
dc.description.abstractThe ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation.en_UK
dc.identifier.citationAslam S, Jennions IK, Samie M, et al., (2020) Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation. IEEE Access, Volume 8, 2020, pp. 31371-31397en_UK
dc.identifier.issn2169-3536
dc.identifier.urihttps://doi.org/10.1109/ACCESS.2020.2973260
dc.identifier.urihttps://dspace.lib.cranfield.ac.uk/handle/1826/15249
dc.language.isoenen_UK
dc.publisherIEEEen_UK
dc.rightsAttribution 4.0 International*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/*
dc.subjectAgeing mechanismen_UK
dc.subjectfield programmable gate array (FPGAen_UK
dc.subjecthardware Trojanen_UK
dc.subjectnegative bias temperature instability (NBTI)en_UK
dc.subjectThreshold voltageen_UK
dc.subjectpropagation delayen_UK
dc.titleIngress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigationen_UK
dc.typeArticleen_UK

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