Rapid prototyping of image contrast enhancement hardware accelerator on FPGAs using high-level synthesis tools

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dc.contributor.authorBilal, Muhammad
dc.contributor.authorHarasani, Wail Ismael
dc.contributor.authorYang, Liang
dc.date.accessioned2024-04-09T12:40:23Z
dc.date.available2024-04-09T12:40:23Z
dc.date.issued2023-09-30
dc.description© The Publisher
dc.description.abstractRapid prototyping tools have become essential in the race to market. In this work, we have explored employing rapid prototyping approach to develop an intellectual property core for real-time contrast enhancement which is a commonly employed image processing task. Specifically, the task involves real-time contrast enhancement of video frames, which is used to repair washed out (overexposed) or darkened (underexposed) appearance. Such scenario is frequently encountered in video footage captured underwater. Since the imaging conditions are not known a priori, the lower and upper limits of the dynamic range of acquired luminance values need to be adaptively determined and mapped to the full range permitted by the allocated bitwidth so that the processed image has a high-contrast appearance. This paper describes a hardware implementation of this operation using contrast stretching algorithm with the help of Simulink high-level synthesis tool using rapid prototyping paradigm. The developed model can be directly used as a drop-in module in larger computer vision systems to enhance Simulink computer vision toolbox capabilities, which does not support this operation for direct FPGA implementation yet. The synthesized core consumes less than 1% of total FPGA slice logic resources while dissipating only 7 mW dynamic power. To this end, look-up table has been employed to implement the division operator which otherwise requires exorbitantly large number of logic resources. Moreover, an online algorithm has been proposed which avoids multiple memory accesses. The hardware module has been tested in a real-time video processing scenario at 100 MHz clock rate and depicts functional accuracy at par with the software while consuming lower logic resources than competitive designs. These results demonstrate that the appropriate use of modern rapid prototyping tools can be highly effective in reducing the development time without compromising the functional accuracy and resource utilization.en_UK
dc.description.sponsorshipThe authors acknowledge the fund from the British Councilen_UK
dc.identifier.citationBilal M, Harasani WI, Yang L. (2023) Rapid prototyping of image contrast enhancement hardware accelerator on FPGAs using high-level synthesis tools. Jordan Journal of Electrical Engineering, Volume 9, Issue 3, September 2023, pp. 322-337en_UK
dc.identifier.issn2409-9600
dc.identifier.urihttps://jjee.ttu.edu.jo/3923/
dc.identifier.urihttp://doi.org/10.5455/jjee.204-1673105856
dc.identifier.urihttps://dspace.lib.cranfield.ac.uk/handle/1826/21159
dc.language.isoen_UKen_UK
dc.publisherScopeMeden_UK
dc.subjectRapid prototypingen_UK
dc.subjectHigh-level synthesisen_UK
dc.subjectAdaptive algorithmen_UK
dc.subjectFPGAen_UK
dc.subjectHardware acceleratoren_UK
dc.subjectHardware-software co-designen_UK
dc.titleRapid prototyping of image contrast enhancement hardware accelerator on FPGAs using high-level synthesis toolsen_UK
dc.typeArticleen_UK
dcterms.dateAccepted2023-03-02

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