Reduced pin-count testing, 3D SICs, time division multiplexing, test access mechanism, simultaneous bidirectional signaling

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dc.contributor.authorSoomro, Iftikhar A.
dc.contributor.authorSamie, Mohammad
dc.date.accessioned2021-06-08T13:29:05Z
dc.date.available2021-06-08T13:29:05Z
dc.date.issued2021-05-17
dc.description.abstract3D Stacked Integrated Circuits (SICs) offer a promising way to cope with the technology scaling; however, the test access requirements are highly complicated due to increased transistor density and a limited number of test channels. Moreover, although the vertical interconnects in 3D SIC are capable of high-speed data transfer, the overall test speed is restricted by scan-chains that are not optimized for timing. Reduced Pin-Count Testing (RPCT) has been effectively used under these scenarios. In particular, Time Division Multiplexing (TDM) allows full utilization of interconnect bandwidth while providing low scan frequencies supported by the scan chains. However, these methods rely on Uni-Directional Signaling (UDS), in which a chip terminal (pin or a TSV) can either be used to transmit or receive data at a given time. This requires that at least two chip terminals are available at every die interface (Tester-Die or Die-Die) to form a single test channel. In this paper, we propose Simultaneous Bi-Directional Signaling (SBS), which allows a chip terminal to be used simultaneously to send and receive data, thus forming a test channel using one pin instead of two. We demonstrate how SBS can be used in conjunction with TDM to achieve reduced pin count testing while using only half the number of pins compared to conventional TDM based methods, consuming only 22.6% additional power. Alternatively, the advantage could be manifested as a test time reduction by utilizing all available test channels, allowing more parallelism and test time reduction down to half compared to UDS-based TDM. Experiments using 45nm technology suggest that the proposed method can operate at up to 1.2 GHz test clock for a stack of 3-dies, whereas for higher frequencies, a binary-weighted transmitter is proposed capable of up to 2.46 GHz test clock.en_UK
dc.identifier.citationSoomro IA, Samie M, Jennions IK. (2021) Reduced Pin-Count Test strategy for 3D Stacked ICs using Simultaneous Bi-directional Signaling based Time Division Multiplexing. IEEE Access, Volume 9, pp. 75892-75904en_UK
dc.identifier.issn2169-3536
dc.identifier.urihttps://doi.org/10.1109/ACCESS.2021.3081359
dc.identifier.urihttps://dspace.lib.cranfield.ac.uk/handle/1826/16740
dc.language.isoenen_UK
dc.publisherIEEEen_UK
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 International*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectReduced pin-count testingen_UK
dc.subject3D SICsen_UK
dc.subjecttime division multiplexingen_UK
dc.subjecttest access mechanismen_UK
dc.subjectsimultaneous bidirectional signalingen_UK
dc.titleReduced pin-count testing, 3D SICs, time division multiplexing, test access mechanism, simultaneous bidirectional signalingen_UK
dc.typeArticleen_UK

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