An analogue method for the analysis of current carrying semiconductor systems

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dc.contributor.author Loeb, H. W.
dc.date.accessioned 2015-08-26T14:34:22Z
dc.date.available 2015-08-26T14:34:22Z
dc.date.issued 1963-09
dc.identifier.uri http://dspace.lib.cranfield.ac.uk/handle/1826/9344
dc.description.abstract In an earlier Internal Technical Memorandum (1) and in subsequent work(2), it has been demonstrated that a particular kind of resistance network, in which non-linear elements are associated with each mesh point, can be made to represent an exact analogue to a non-degenerate semiconductor system in the equilibrium or quasi-equilibrium state. The term !exact' in this context implies that the difference equation which governs the potential distribution in the network becomes identical, for the limit of vanishing mesh interval, with the differential equation for the electrostatic potential within the semiconductor system, i.e. the Shockley-Poisson equation. From this type of analogue network information concerning the variation of maximum field intensity and of junction capacitance with applied bias voltages can be obtained for one, two and three dimensional configurations of p and n type regions of arbitrary geometry and impurity concentration profiles. One limitation to the applicability of the analogue technique arises from the restriction to quasi-equilibrium conditions. This restriction precludes the investigation of situations in which current flow contributions to the carrier concentration pattern become significant - for example, in the case of strongly forward biassed p-n junctions, and of p-i-n junctions and transistors operating at high injection levels. In the present paper, the problems involved in an extension of the basic analogue method to the treatment of non-equilibrium situations are examined, and means for their solution are discussed. A review of the methods previously described and an illustration of the nature of their limitations is given in Section 2. This is followed, in Sections 3 to 7, by a detailed treatment of the case of a current carrying semiconductor system in one dimension which leads to a theoretically possible realization in terms of resistancenetwork/ analogue computer techniques, which is, however, too complex to. be considered practical. Section 8 discusses means for the simplification of the proposed schemes and leads to the description of a relatively simple system in which a significant reduction in equipment complexity has been made possible by the adoption of an operating mode based upon an iterative process of successive approximations. The extension of the technique to three dimensions is outlined in Section 9. en_UK
dc.language.iso en en_UK
dc.publisher College of Aeronautics en_UK
dc.relation.ispartofseries 3 en_UK
dc.relation.ispartofseries COA/M-3 en_UK
dc.title An analogue method for the analysis of current carrying semiconductor systems en_UK
dc.type Report en_UK


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