CERES :: Browsing by Author "Samie, Mohammad"

Browsing by Author "Samie, Mohammad"

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Open Access
A Carrier Signal Approach for Intermittent Fault Detection and Health Monitoring for Electronics Interconnections System
(Science and Information Organisation, 2015-12-01) Ahmad, Syed Wakil; Perinpanayagam, Suresh; Jennions, Ian K.; Samie, Mohammad
Abstract: Intermittent faults are completely missed out by traditional monitoring and detection techniques due to non-stationary nature of signals. These are the incipient events of a precursor of permanent faults to come. Intermittent faults in electrical interconnection are short duration transients which could be detected by some specific techniques but these do not provide enough information to understand the root cause of it. Due to random and non-predictable nature, the intermittent faults are the most frustrating, elusive, and expensive faults to detect in interconnection system. The novel approach of the author injects a fixed frequency sinusoidal signal into electronics interconnection system that modulates intermittent fault if persist. Intermittent faults and other channel effects are computed from received signal by demodulation and spectrum analysis. This paper describes technology for intermittent fault detection, and classification of intermittent fault, and channel characterization. The paper also reports the functionally tests of computational system of the proposed methods. This algorithm has been tested using experimental setup. It generate an intermittent signal by external vibration stress on connector and intermittency is detected by acquiring and processing propagating signal. The results demonstrate to detect and classify intermittent interconnection and noise variations due to intermittency. Monitoring the channel in-situ with low amplitude, and narrow band signal over electronics interconnection between a transmitter and a receiver provides the most effective tool for continuously watching the wire system for the random, unpredictable intermittent faults, the precursor of failure. - See more at: http://thesai.org/Publications/ViewPaper?Volume=6&Issue=12&Code=ijacsa&SerialNo=20#sthash.8RXsdW0t.dpuf
Open Access
Computationally efficient, real-time, and embeddable prognostic techniques for power electronics
(IEEE, 2014-10-02) Alghassi, Alireza; Perinpanayagam, Suresh; Samie, Mohammad
Power electronics are increasingly important in new generation vehicles as critical safety mechanical subsystems are being replaced with more electronic components. Hence, it is vital that the health of these power electronic components is monitored for safety and reliability on a platform. The aim of this paper is to develop a prognostic approach for predicting the remaining useful life of power electronic components. The developed algorithms must also be embeddable and computationally efficient to support on-board real-time decision making. Current state-of-the-art prognostic algorithms, notably those based on Markov models, are computationally intensive and not applicable to real-time embedded applications. In this paper, an isolated-gate bipolar transistor (IGBT) is used as a case study for prognostic development. The proposed approach is developed by analyzing failure mechanisms and statistics of IGBT degradation data obtained from an accelerated aging experiment. The approach explores various probability distributions for modeling discrete degradation profiles of the IGBT component. This allows the stochastic degradation model to be efficiently simulated, in this particular example ~1000 times more efficiently than Markov approaches.
Open Access
Cross-domain self-authentication based consortium blockchain for autonomous valet parking system
(IEEE, 2022-08-18) Hua, Lei; Jiang, Haobin; Xiao, Jian; Samie, Mohammad
This paper proposed a cross-domain self-authentication scheme to address the “information isolated island” problem of users’ identities storage in servers and the “redundant registration problem” of users’ identities for Autonomous Valet Parking (AVP). This scheme adopts a decentralized anonymous authentication method to relieve the authentication center’s service load. Users are segregated into two categories to increase authentication efficiency: inexperienced and regular users. For the former, the paper explores a self-authentication mechanism based on verification parameters. Then, its valid personal information, pseudonym and public key, were stored in a consortium blockchain (PseIDChain) as the transaction records so that they can be securely shared among servers located in different domains. For the latter (regular users), an efficient authentication mechanism, searching users’ personal information on PseIDChain by the smart contract, was proposed. Security proof and simulation results show that the designed scheme has superior security to the existing schemes. Its authentication efficiency is 80.29% and 50.45% higher than the traditional anonymous and batch authentication schemes.
Open Access
Delay-based true random number generator in sub-nanomillimeter IoT devices
(MDPI, 2020-05-15) Randa, Maulana; Samie, Mohammad; Jennions, Ian K.
True Random Number Generators (TRNGs) use physical phenomenon as their source of randomness. In electronics, one of the most popular structures to build a TRNG is constructed based on the circuits that form propagation delays, such as a ring oscillator, shift register, and routing paths. This type of TRNG has been well-researched within the current technology of electronics. However, in the future, where electronics will use sub-nano millimeter (nm) technology, the components become smaller and work on near-threshold voltage (NTV). This condition has an effect on the timing-critical circuit, as the distribution of the process variation becomes non-gaussian. Therefore, there is an urge to assess the behavior of the current delay-based TRNG system in sub-nm technology. In this paper, a model of TRNG implementation in sub-nm technology was created through the use of a specific Look-Up Table (LUT) in the Field-Programmable Gate Array (FPGA), known as SRL16E. The characterization of the TRNG was presented and it shows a promising result, in that the delay-based TRNG will work properly, with some constraints in sub-nm technology
Open Access
Design for prognostics and security in field programmable gate arrays (FPGAs).
(Cranfield University, 2020-03) Aslam, Sohaib; Jennions, Ian K.; Samie, Mohammad
There is an evolutionary progression of Field Programmable Gate Arrays (FPGAs) toward more complex and high power density architectures such as Systems-on- Chip (SoC) and Adaptive Compute Acceleration Platforms (ACAP). Primarily, this is attributable to the continual transistor miniaturisation and more innovative and efficient IC manufacturing processes. Concurrently, degradation mechanism of Bias Temperature Instability (BTI) has become more pronounced with respect to its ageing impact. It could weaken the reliability of VLSI devices, FPGAs in particular due to their run-time reconfigurability. At the same time, vulnerability of FPGAs to device-level attacks in the increasing cyber and hardware threat environment is also quadrupling as the susceptible reliability realm opens door for the rogue elements to intervene. Insertion of highly stealthy and malicious circuitry, called hardware Trojans, in FPGAs is one of such malicious interventions. On the one hand where such attacks/interventions adversely affect the security ambit of these devices, they also undermine their reliability substantially. Hitherto, the security and reliability are treated as two separate entities impacting the FPGA health. This has resulted in fragmented solutions that do not reflect the true state of the FPGA operational and functional readiness, thereby making them even more prone to hardware attacks. The recent episodes of Spectre and Meltdown vulnerabilities are some of the key examples. This research addresses these concerns by adopting an integrated approach and investigating the FPGA security and reliability as two inter-dependent entities with an additional dimension of health estimation/ prognostics. The design and implementation of a small footprint frequency and threshold voltage-shift detection sensor, a novel hardware Trojan, and an online transistor dynamic scaling circuitry present a viable FPGA security scheme that helps build a strong microarchitectural level defence against unscrupulous hardware attacks. Augmented with an efficient Kernel-based learning technique for FPGA health estimation/prognostics, the optimal integrated solution proves to be more dependable and trustworthy than the prevalent disjointed approach.
Open Access
Design of hardware-orientated security towards trusted electronics.
(Cranfield University, 2020-07) Randa, Maulana; Jennions, Ian K.; Samie, Mohammad
While the Internet of Things (IoT) becomes one of the critical components in the cyber-physical system of industry 4.0, its root of trust still lacks consideration. The purpose of this thesis was to increase the root of trust in electronic devices by enhance the reliability, testability, and security of the bottom layer of the IoT system, which is the Very Large-Scale Integration (VLSI) device. This was achieved by implement a new class of security primitive to secure the IJTAG network as an access point for testing and programming. The proposed security primitive expands the properties of a Physically Unclonable Function (PUF) to generate two different responses from a single challenge. The development of such feature was done using the ring counter circuit as the source of randomness of the PUF to increase the efficiency of the proposed PUF. The efficiency of the newly developed PUF was measured by comparing its properties with the properties of a legacy PUF. The randomness test done for the PUF shows that it has a limitation when implemented in sub-nm devices. However, when it was implemented in current 28nm silicon technology, it increases the sensitivity of the PUF as a sensor to detect malicious modification to the FPGA configuration file. Moreover, the efficiency of the developed bimodal PUF increases by 20.4% compared to the legacy PUF. This shows that the proposed security primitive proves to be more dependable and trustworthy than the previously proposed approach.
Open Access
Developing prognostic models using duality principles for DC-to-DC converters
(IEEE, 2019-12-02) Samie, Mohammad; Perinpanayagam, Suresh; Alghassi, Alireza; Motlagh, Amir M. S.; Kapetanios, Epaminondas
Within the field of Integrated System Health Management, there is still a lack of technological approaches suitable for the creation of adequate prognostic model for large applications whereby a number of similar or even identical subsystems and components are used. Existing similarity among a number of different systems, which are comprised of similar components but with different topologies, can be employed to assign the prognostics of one system to other systems using an inference engine. In the process of developing prognostics, this approach will thereby save resources and time. This paper presents a radically novel approach for building prognostic models based on system similarity in cases where duality principle in electrical systems is utilized. In this regard, unified damage model is created based on standard Tee/Pi models, prognostics model based on transfer functions, and remaining useful life (RUL) estimator based on how energy relaxation time of system is changed due to degradation. An advantage is that the prognostic model can be generalized such that a new system could be developed on the basis and principles of the prognostic model of other systems. Simple electronic circuits, dc-to-dc converters, are to be used as an experiment to exemplify the potential success of the proposed technique validated with prognostics models from particle filter.
Open Access
Evaluation of CAN bus security challenges
(MDPI, 2020-04-21) Bozdal, Mehmet; Samie, Mohammad; Aslam, Sohaib; Jennions, Ian
The automobile industry no longer relies on pure mechanical systems; instead, it benefits from many smart features based on advanced embedded electronics. Although the rise in electronics and connectivity has improved comfort, functionality, and safe driving, it has also created new attack surfaces to penetrate the in-vehicle communication network, which was initially designed as a close loop system. For such applications, the Controller Area Network (CAN) is the most-widely used communication protocol, which still suffers from various security issues because of the lack of encryption and authentication. As a result, any malicious/hijacked node can cause catastrophic accidents and financial loss. This paper analyses the CAN bus comprehensively to provide an outlook on security concerns. It also presents the security vulnerabilities of the CAN and a state-of-the-art attack surface with cases of implemented attack scenarios and goes through different solutions that assist in attack prevention, mainly based on an intrusion detection system (IDS)
Open Access
Experiment results of failure progression from low power wires
(Elsevier, 2017-03-02) Samie, Mohammad; Alghassi, Alireza; Jennions, Ian K.
Despite various studies that have been conducted so far on the failure of high power cables, failure progression in low power cables, wires and interconnections have not been well understood yet. In general, it is hypothesised that failures of wires are progressed from random intermittent failures that are gradually developed as hard faults. This paper aims to present a test rig and possible test techniques that can be used for testing the failure progression of wires and interconnections. Research presented in this paper is based on tools, equipment and techniques that facilitate various ageing mechanisms needed to capture proper and right failure patterns from low power cables, wires and interconnections.
Open Access
Experiment results of failure progression from low power wires
(Elsevier, 2017-03-02) Samie, Mohammad; Alghassi, Alireza; Jennions, Ian K.
Despite various studies that have been conducted so far on the failure of high power cables, failure progression in low power cables, wires and interconnections have not been well understood yet. In general, it is hypothesised that failures of wires are progressed from random intermittent failures that are gradually developed as hard faults. This paper aims to present a test rig and possible test techniques that can be used for testing the failure progression of wires and interconnections. Research presented in this paper is based on tools, equipment and techniques that facilitate various ageing mechanisms needed to capture proper and right failure patterns from low power cables, wires and interconnections. Paper originally presented at the 5th International Conference in Through-life Engineering Services Cranfield University, 1st and 2nd November 2016.
Open Access
Fault Tolerance Enhance DC-DC Converter Lifetime Extension
(Elsevier, 2017-03-02) Alghassi, Alireza; Soulatiantork, Payam; Samie, Mohammad; Uriondo Del Pozo, Adrian; Perinpanayagam, Suresh; Faifer, M.
One of the most crucial renewable energy sources today is solar energy. Power convertors play an important role in adjusting the output voltage or current of photovoltaic (PV) systems. Using efficient and reliable switches for power converters and inverters is crucial for enhancing the safety and reliability of a platform. Generally, power converters suffer from failure mechanisms, such as wire bond fatigue, wire bond lift up, solder fatigue and loose gate control voltage, which mainly occur in power switches. In this paper, the junction temperature of the Insulated Gate Bipolar Transistor (IGBT) acting as a power switch used in the Impedance-Source DC-DC converter is estimated using an electro-thermal model in order to develop an adaptive thermal stress control (ATSC). The proposed stress control adjusts reference input of the PI control to extend the life expectancy of the device under the mission. The accuracy of results present using The Modified Coffin-Manson Law has been used to determine the life of IGBT and the lifetime has been successfully increased base on implementing imperative ATSC and comparing the result with the constant reference input of the PI controller. The result integrates with converter health management to develop advanced intelligent predictive maintenance.
Open Access
Hardware trojan enabled denial of service attack on CAN bus
(Elsevier, 2018-11-02) Bozdal, Mehmet; Randa, Maulana; Samie, Mohammad; Jennions, Ian
The trend of technological advances in the vehicle industry illustrates that future cars would have added functionalities with smart features, better connectivity and autonomous behaviour. These naturally involve a higher number of Electronic Control Units (ECUs) being connected using existing conventional in-vehicle network protocols such as Controller Area Network (CAN). In this context, security of systems is now becoming a major concern while industry’s primary interest in the manufacturing of cars is reliability and safety. It is now in daily news that smart cars are being hacked due to weaknesses in their embedded electronics that provides ways of hardware attacks [1] [2]. Hardware Trojan (HT) is the threat that has been recently recognised as one of the primary sources of backdoor access that enables hackers to attack systems. As trouble, HT remains silent until a rare function/event triggers it for activation. This paper contributes to the challenge of demonstration of disruption in CAN buses raised from hidden Hardware Trojan. In this regard, it is presented how just a small size Hardware Trojan disrupts the CAN bus communication without an adversary having physical access to the bus. The attack is neither detectable via frame analysis, nor can be prevented via network segmentation; additionally, a rare triggering mechanism activates HT to process untraceable faults.
Open Access
Hardware trojans and smart manufacturing – a hardware security perspective
(IOS Press, 2018-12-01) Aslam, Sohaib; Samie, Mohammad; Jennions, Ian K.
Integrated Circuits (ICs) are the cardinal elements of modern electrical, electronic and electro-mechanical systems. Amid global outsourcing of ICs' design and fabrication and their growing applications in smart manufacturing or Industrie 4.0, various hardware security threats and issues of trust have also emerged. IC piracy, counterfeiting, and hardware Trojans (HTs) are some of the key hardware threats that merit the attention of manufacturing community. It is worth noting that the lower abstraction levels (ICs) are falsely assumed to operate securely. The proposition, therefore, is that if an operating system (higher abstraction level) is considered to be secure while operating on a compromised IC (lower abstraction level), would it be prudent to regard this implementation as secure? The purpose of this paper is to highlight IC level threats with an emphasis on hardware Trojans that pose a significant threat to smart manufacturing environment in the wake of Industrial Internet of Things (IIoT).
Open Access
Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation
(IEEE, 2020-02-11) Aslam, Sohaib; Jennions, Ian K.; Samie, Mohammad; Perinpanayagam, Suresh; Fang, Yisen
The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation.
Open Access
Integrating simultaneous bi-direction signalling in the test fabric of 3D stacked integrated circuits.
(Cranfield University, 2021-07) Soomro, Iftikhar Ahmed; Samie, Mohammad; Jennions, Ian K.
The world has seen significant advancements in electronic devices’ capabilities, most notably the ability to embed ultra-large-scale functionalities in lightweight, area and power-efficient devices. There has been an enormous push towards quality and reliability in consumer electronics that have become an indispensable part of human life. Consequently, the tests conducted on these devices at the final stages before these are shipped out to the customers have a very high significance in the research community. However, researchers have always struggled to find a balance between the test time (hence the test cost) and the test overheads; unfortunately, these two are inversely proportional. On the other hand, the ever-increasing demand for more powerful and compact devices is now facing a new challenge. Historically, with the advancements in manufacturing technology, electronic devices witnessed miniaturizing at an exponential pace, as predicted by Moore’s law. However, further geometric or effective 2D scaling seems complicated due to performance and power concerns with smaller technology nodes. One promising way forward is by forming 3D Stacked Integrated Circuits (SICs), in which the individual dies are stacked vertically and interconnected using Through Silicon Vias (TSVs) before being packaged as a single chip. This allows more functionality to be embedded with a reduced footprint and addresses another critical problem being observed in 2D designs: increasingly long interconnects and latency issues. However, as more and more functionality is embedded into a small area, it becomes increasingly challenging to access the internal states (to observe or control) after the device is fabricated, which is essential for testing. This access is restricted by the limited number of Chip Terminals (IC pins and the vertical Through Silicon Vias) that a chip could be fitted with, the power consumption concerns, and the chip area overheads that could be allocated for testing. This research investigates Simultaneous Bi-Directional Signaling (SBS) for use in Test Access Mechanism (TAM) designs in 3D SICs. SBS enables chip terminals to simultaneously send and receive test vectors on a single Chip Terminal (CT), effectively doubling the per-pin efficiency, which could be translated into additional test channels for test time reduction or Chip Terminal reduction for resource efficiency. The research shows that SBS-based test access methods have significant potential in reducing test times and/or test resources compared to traditional approaches, thereby opening up new avenues towards cost-effectiveness and reliability of future electronics.
Open Access
Layered security for IEEE 1687 using a Bimodal Physically Unclonable Function
(Elsevier, 2018-11-02) Randa, Maulana; Bozdal, Mehmet; Samie, Mohammad; Jennions, Ian K.
In this paper, a layered security mechanism for IEEE 1687 is proposed using a new class of physically unclonable function (PUF) called Bimodal PUF. It moves beyond the conventional single-challenge single-response PUF by introducing a second response to the PUF gained from the same single challenge. As an advantage, a double-response PUF forms two-layer security solution, one at the hardware layer by limiting the access to the embedded instrument and the second one for the data layer by securing the output data that needs to be transmitted. Experiments conducted with FPGA show that such advantages come in place at a small silicon area overhead, up to 1.4%, for a 64-bit security key. This is known to be sufficient enough to resist brute-force and machine learning attack.
Open Access
A novel intermittent fault detection algorithm and health monitoring for electronic interconnections
(Institute of Electrical and Electronics Engineers, 2016-02-19) Syed, Wakil Amad; Perinpanayagam, Suresh; Samie, Mohammad; Jennions, Ian K.
There are various occurrences and root causes that result in no-fault-found (NFF) events but an intermittent fault (IF) is the most frustrating. This paper describes the challenging and most important area of an IF detection and health monitoring that focuses toward NFF situation in electronics interconnections. The experimental work focuses on mechanically-induced intermittent conditions in connectors. This paper illustrates a test regime, which can be used to repeatedly reproduce intermittence in electronic connectors, while subjected to vibration. A novel algorithm is used to detect an IF in interconnection. It sends a sine wave and decodes the received signal for intermittent information from the channel. This algorithm has been simulated to capture an IF signature using PSpice (electronic circuit simulation software). A simulated circuit is implemented for practical verification. However, measurements are presented using an oscilloscope. The results of this experiment provide an insight into the limitations of existing test equipment and requirements for future IF detection techniques. Aside from scheduled maintenance, this paper considers the possibility for in-service intermittent detection to be built into future systems, i.e., can IFs be captured without external test gear?
Open Access
Principle of Duality on Prognostics
(SAI Organization, 2015-06-30) Samie, Mohammad; Motlagh, Amir M. S.; Alghassi, Alireza; Perinpanayagam, Suresh; Kapetanios, Epaminondas
he accurate estimation of the remaining useful life (RUL) of various components and devices used in complex systems, e.g., airplanes remain to be addressed by scientists and engineers. Currently, there area wide range of innovative proposals put forward that intend on solving this problem. Integrated System Health Management (ISHM) has thus far seen some growth in this sector, as a result of the extensive progress shown in demonstrating feasible and viable techniques. The problems related to these techniques were that they often consumed time and were too expensive and resourceful to develop. In this paper we present a radically novel approach for building prognostic models that compensates and improves on the current prognostic models inconsistencies and problems. Broadly speaking, the new approach proposes a state of the art technique that utilizes the physics of a system rather than the physics of a component to develop its prognostic model. A positive aspect of this approach is that the prognostic model can be generalized such that a new system could be developed on the basis and principles of the prognostic model of another system. This paper will mainly explore single switch dc-to-dc converters which will be used as an experiment to exemplify the potential success that can be discovered from the development of a novel prognostic model that can efficiently estimate the remaining useful life of one system based on the prognostics of its dual system.
Open Access
Reduced pin-count testing, 3D SICs, time division multiplexing, test access mechanism, simultaneous bidirectional signaling
(IEEE, 2021-05-17) Soomro, Iftikhar A.; Samie, Mohammad
3D Stacked Integrated Circuits (SICs) offer a promising way to cope with the technology scaling; however, the test access requirements are highly complicated due to increased transistor density and a limited number of test channels. Moreover, although the vertical interconnects in 3D SIC are capable of high-speed data transfer, the overall test speed is restricted by scan-chains that are not optimized for timing. Reduced Pin-Count Testing (RPCT) has been effectively used under these scenarios. In particular, Time Division Multiplexing (TDM) allows full utilization of interconnect bandwidth while providing low scan frequencies supported by the scan chains. However, these methods rely on Uni-Directional Signaling (UDS), in which a chip terminal (pin or a TSV) can either be used to transmit or receive data at a given time. This requires that at least two chip terminals are available at every die interface (Tester-Die or Die-Die) to form a single test channel. In this paper, we propose Simultaneous Bi-Directional Signaling (SBS), which allows a chip terminal to be used simultaneously to send and receive data, thus forming a test channel using one pin instead of two. We demonstrate how SBS can be used in conjunction with TDM to achieve reduced pin count testing while using only half the number of pins compared to conventional TDM based methods, consuming only 22.6% additional power. Alternatively, the advantage could be manifested as a test time reduction by utilizing all available test channels, allowing more parallelism and test time reduction down to half compared to UDS-based TDM. Experiments using 45nm technology suggest that the proposed method can operate at up to 1.2 GHz test clock for a stack of 3-dies, whereas for higher frequencies, a binary-weighted transmitter is proposed capable of up to 2.46 GHz test clock.
Open Access
Stochastic RUL calculation enhanced with TDNN-based IGBT failure modeling
(Institute of Electrical and Electronics Engineers, 2016-05-30) Alghassi, Alireza; Perinpanayagam, Suresh; Samie, Mohammad
Power electronics are widely used in the transport and energy sectors. Hence, the reliability of these power electronic components is critical to reducing the maintenance cost of these assets. It is vital that the health of these components is monitored for increasing the safety and availability of a system. The aim of this paper is to develop a prognostic technique for estimating the remaining useful life (RUL) of power electronic components. There is a need for an efficient prognostic algorithm that is embeddable and able to support on-board real-time decision-making. A time delay neural network (TDNN) is used in the development of failure modes for an insulated gate bipolar transistor (IGBT). Initially, the time delay neural network is constructed from training IGBTs' ageing samples. A stochastic process is performed for the estimation results to compute the probability of the health state during the degradation process. The proposed TDNN fusion with a statistical approach benefits the probability distribution function by improving the accuracy of the results of the TDDN in RUL prediction. The RUL (i.e., mean and confidence bounds) is then calculated from the simulation of the estimated degradation states. The prognostic results are evaluated using root mean square error (RMSE) and relative accuracy (RA) prognostic evaluation metrics.