Test time reduction of 3D stacked ICs using ternary coded simultaneous bi-directional signaling in parallel test ports

In order to meet the increasing demand for more performance with reduced power consumption and chip formfactor, semiconductor manufacturing is moving towards 3D Stacked Integrated Circuits (SIC). One of the challenges in bringing this technology into realization is the complicated test accessibility requirements of 3D chips, which apart from having adequate defect coverage, should also have minimal test time. A major limiting factor in test time improvement of ICs is the number of chip terminals, such as pins or Through Silicon Vias (TSVs) available for bulk vector transport in testing. In the conventional design, a chip terminal is only used to either send or receive data at any given time. In this paper, a test accessibility architecture based on ternary encoded Simultaneous Bi- Directional Signaling (SBS), intended for use in parallel Test Access Mechanism (TAM) in System on Chip (SoC) based designs, is proposed. This method enables the use of chip terminals to simultaneously send and receive test vectors, effectively doubling the per-pin efficiency during testing. Experiments show that this technique reduces the Overall Test Time (OTT) by up to 53.6% as compared to conventional TAM design methods.