Robust Time Synchronization for Industrial Internet of Things by H∞ Output Feedback Control

Precise timing over timestamped packet-exchange communication is an enabling technology in the mission-critical industrial Internet of Things (IIoT), particularly when satellite-based timing is unavailable. The main challenge is to ensure timing accuracy when the clock synchronization system is subject to disturbances caused by the drifting frequency, time-varying delay, jitter, and timestamping uncertainty. In this work, a robust packet-coupled oscillators (R-PkCOs) protocol is proposed to reduce the effects of perturbations manifested in the drifting clock, timestamping uncertainty, and delays. First, in the spanning-tree clock topology, time synchronization between an arbitrary pair of clocks is modeled as a state-space model, where clock states are coupled with each other by one-way timestamped packet exchange (referred to as packet coupling), and the impacts of both drifting frequency and delays are modeled as disturbances. A static output controller is adopted to adjust the drifting clock. The $H_{\infty }$ robust control design solution is proposed to guarantee that the ratio between the modulus of synchronization precision and the magnitude of the disturbances are always less than a given value. Therefore, the proposed time synchronization protocol is robust against the disturbances, which means that the impacts of drifting frequency and delays on the synchronization accuracy are limited. The one-hour experimental results demonstrate that the proposed R-PkCO’s protocol can realize time synchronization with the precision of 6 $\mu \text{s}$ in a 21-node IEEE 802.15.4 network. This work has widespread impacts in the process automation of automotive, mining, oil, and gas industries.


I. INTRODUCTION
O VER the last decade, the rapid proliferation of Internet of Things (IoT) has been instrumental in the digital manufacturing revolution (fourth industrial revolution), and a new era of the Industrial IoT (IIoT) has emerged with different requirements to traditional IoT systems. Precise timing is one of the most sought after IIoT attributes in mission-critical industrial applications, especially those that have control loops commonly found in chemical engineering and precision manufacturing. This means that the time-sensitive wireless IIoT networks have stringent requirements on the reliability and the real time of data transmission and control operation command [1], [2]. Hence, the enabling technology time synchronization is required to provide a common sense of timing among wireless nodes.
Due to the inherent low energy consumption [3] and reliability [4] characteristics of spanning-tree topology, it has been widely used for time synchronization [5]. Also, inspired by the synchrony of fireflies' flashing [6], a typical model, pulse-coupled oscillators (PCO), is proposed in natural and physical science communities [7]. Thanks to its simplicity and scalability, this model is particularly suitable for resource-constrained wireless sensor networks [8]. However, the assumptions of PCO (e.g., failure of producing the physical Pulse signal, and no delays exist during the firing information (i.e., Pulse) exchange among oscillators) limit its application in off-the-shelf wireless networks. Thus, it needs to be improved for employment in industrial applications.
In IEEE 802. 15.4 (also known as ZigBee) [9] networks, the PCO's Pulse waveform cannot be generated from the medium access control (MAC) layer. Nevertheless, the wireless packet can be treated as a substitute solution for the Pulse signal. Moreover, the periodic resetting feature of the clock model is similar to the firing-resetting procedure in PCO [10]. Therefore, our earlier work [11] proposed the packet-coupled oscillators (PkCOs) model, where the Sync packet (from a transmitter) is utilized for reporting the firing information to other nodes. In this work, we utilize the H ∞ method for selecting the PkCOs [11] parameters. Thus, a robust PkCOs (R-PkCOs) protocol is proposed for the spanning-tree clock synchronization network (e.g., Fig. 1). 1

A. Related Work
As a result of the widespread importance of synchronization, it has been studied in various communities, and many synchronization protocols have been proposed for wireless networks. In the communication engineering community, from the perspective of the packet-exchange strategy, these algorithms can be categorized into two types, which are the 1 We refer the reader to Section II for more details of Fig. 1. 2327-4662 c 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information. receiver-to-receiver (e.g., RBS [12]) and sender-to-receiver 2 (e.g., TPSN [13], RMTS [14], and PISync [15]) synchronization protocols. The principle of these algorithms is to measure the clock offset (which is referred to as the time difference between two connected clocks) through packet exchange during each synchronization cycle T; and the employment of the offset estimate to the local clock lets a network achieve time synchronization.
For the RBS and TPSN algorithms, during a cycle T, several timestamped packets are sent and received between a pair of nodes. However, once these two protocols are employed to the large-scale wireless network, the offset estimate suffers from a delay jitter, owing to factors, such as packet collisions and retransmission. Utilizing inaccurate offset estimates reduce the synchronization performance of RBS and TPSN in the multihop network. In addition, since the radio frequency (RF) transceiver is the most power consumption unit in a wireless node [16], frequent RF communication poses a challenge on the energy-constrained node.
In many mission-critical industrial applications, the slot-based contention-free packet transmission mechanism is used to guarantee that the packet-exchange delay is almost deterministic, and thus to ensure a high Quality of Service (QoS) [11], [17]. Thanks to this feature, instead of transmitting multiple wireless packets, the one-way sender-to-receiver protocol (also referred to as the flooding algorithm) only needs one packet to obtain a more accurate clock offset, thereby leading to better synchronization precision. Moreover, two timestamps are required in the flooding algorithm: one is generated when a transmitter sends a packet, and the other one is on the reception of the packet on a receiver.
The IEEE 802.15.4 standard provides the beacon-enabled operation on the MAC layer, and the corresponding superframe [consisting of contention access period (CAP), contention-free period (CFP), and inactive period] offers hybrid transmission mechanisms. Specifically, during CAP, all nodes need to contend for the access of a frequency channel. Instead, the CFP guarantees a specific slot to each node. The control packet (i.e., Sync) of R-PkCOs is sent in CFP to guarantee low-latency 2 The sender-to-receiver synchronization algorithm can be further classified into two kinds, namely, the one-way (e.g., RMTS and PISync) and two-way (e.g., TPSN) exchange protocols. transmission and a tiny jitter. Furthermore, the R-PkCO's protocol only demands one timestamp (which is generated upon the reception of a Sync packet), and the packet itself represents the clock firing information. This feature can further reduce the effects of timestamping uncertainty, improve offset estimate accuracy, and enhance synchronization performance, compared to the flooding protocol.
In addition to the packet-exchange strategy, using advanced processing techniques (e.g., maximum-likelihood estimation [18], and linear least squares regression [19]) is an alternative way to improve time synchronization precision. Typically, the clock frequency difference may let the achieved synchronization lose gradually [20]. The clock skew 3 correction method allows the longer synchronized state and the less frequent strychninization among coupled clocks.
In [14] and [18], the maximum-likelihood estimation method is used to estimate the clock skew and also to obtain a more accurate clock offset; however, the resource-limited node (with a 32-bit microprocessor) has difficulty in handling such a complex processing technology. Thus, in [19], the estimation procedure of clock offset and skew via the linear least squares regression method is on the cluster head, which is equipped with a powerful processor, rather than on the local node. Even though Tian et al. [21] adopted the lower computational complexity solution (i.e., exponential moving average) to calculate the clock skew, the proposed synchronization algorithm is still evaluated on FPGA-based wireless nodes. Moreover, Yildirim et al. [15] stated that a proportional-integral controller is utilized in PISync, from (3) and (6) of this cited work, the used controlling strategy actually is a proportional controller. In this article, a static output feedback controller is adopted for clock correction, and it demands fewer computational overhead, compared to the above processing methods (e.g., [18] and [21]).
It is notable that, although the works cited above take the nonidentical [14], [21] and drifting [15] clock frequency, and packet-exchange delay [11], [14], [15], [21] into consideration, only the theoretical analysis of a synchronization protocol is presented. In addition, the logical (or virtual) clock, which is an affine function of the physical clock in Fig. 2(a), is used in the protocol analysis and hardware experiments [14], [15], [21]. Thus, the processing delay, which occurs during the data processing, and the employment of offset and skew estimates, are missing. Overall, there still exists a lack of theoretical design of synchronization protocol parameters, with the effects of clock noises and external disturbances (from packet-exchange and processing delays). This motivates us to use the H ∞ control solution for parameter selection of the R-PkCOs protocol and extending our previous researches [8], [11].

B. Contributions and Paper Organization
In this article, we propose a robust PkCOs protocol to correct both clock skew and offset for improving synchronization precision, subject to the impacts of drifting frequency, and external perturbations from delays. In addition to using the slot-based one-way Sync packet transmission mechanism, the H ∞ control method is also adopted to guide the R-PkCOs parameter selection, for letting clock and delay noises possess a small effect on the synchronization accuracy. Specifically, through designing the static controller, the ratio between the modulus of the achieved synchronization precision and the magnitude of the noises is always less than a given value. Thus, the robustness of R-PkCOs is guaranteed, in the presence of internal clock and external delay noises. The one-hour experimental results show that the proposed R-PkCOs protocol is capable of achieving time synchronization with the precision of 6 ms in a spanning-tree clock network.
The remainder of this article is organized as follows. Section II describes the R-PkCOs model, which consists of the mathematical modeling of a nonidentical and drifting embedded clock, and the packet-coupled synchronization scheme. Then, Section III presents the H ∞ output feedback control for the R-PkCOs time synchronization method. The simulation and experimental results are, respectively, shown in Sections IV and V. Eventually, Section VI concludes this work.

II. ROBUST PACKET-COUPLED OSCILLATORS
The spanning-tree clock synchronization network, for example, in Fig. 1, can be described by a directed graph G = (V, E, A), 4 where V = {0, 1, . . . , N} denotes a set of nodes, and a set of edges E induced by the adjacency matrix A. The network is composed of a root node (i.e., i = 0) and a set of sensor nodes represented by N = {i : i ∈ V, i ≥ 1}. The root node is unique and is equipped with a global positioning system (GPS) clock to provide the reference time to all the sensor nodes in a network. For the ith sensor node, it corrects the local clock, upon the reception of a Sync packet from the parent node.

A. Modeling of Drifting Embedded Clocks
In the embedded system, the real-time clock (RTC) module of each node is implemented by a counter register, which is driven by a crystal oscillator [see Fig. 2(a)]. As shown in Fig. 2(b), once the counter reaches the predefined value in the threshold register, it is reset and counts from zero again; in the meantime, an interrupt (i.e., IRQ) signal is sent to the processor for triggering an event (e.g., sending a wireless packet for synchronization purposes). This periodic resetting feature can be modeled as an oscillator running on the unit circle [see Fig. 2(c)]. Once the oscillator's time variable P i reaches the threshold, the oscillator fires (i.e., a Sync packet is generated and transmitted in CFP) and P i are reset to zero, after which it increases again. Note that since Sync itself contains the clock firing information, there is no need to generate a timestamp when sending the packet. This helps R-PkCOs reduce the effects of timestamping uncertainty.
Referring first to the case of an ideal embedded clock on the root node, the time variable P 0 [n] can be utilized to model the clock's periodic resetting behavior, and P 0 [n] at the nth event satisfies the following form: where τ 0 is the nominal (clock update) period, and the nominal frequency f 0 of the perfect clock is equal is the clock's threshold; in practice, ϕ 0 [k] may be a constant value, which equals the time synchronization cycle T. k is the number of clock resetting from n = 0 to the nth event, and it also represents that the clock is at the kth synchronization cycle. In addition, we assume that the perfect clock updates m 0 times in a cycle T (i.e., ϕ 0 = m 0 τ 0 ) [11]. Thus, k can be obtained from the floor function k = n/m 0 . However, due to the manufacturing tolerance and environmental temperature, the ith clock's time variable P i [n] cannot be the same as P 0 [n] of the perfect clock. Through modeling the random noise from the phase variation φ i [n]/2π f 0 and the clock frequency deviation By substituting (1) and (2) into (3), calculating the offset difference between two consecutive clock events and expanding the clock offset and skew from n-dimension into k-dimension [22], the drifting embedded clock (2) is remodeled as where ω θ i [k] and ω γ i [k] are the Gaussian random noise processes, and the corresponding variances are σ 2 θ i and σ 2 γ i [23]. The matrix form of (4) is also obtained

B. Packet-Coupled Synchronization Scheme
In order to reduce the effects of packet-exchange delay jitter on the synchronization precision, this work allocates the Sync packet transmission event to a specific time slot (in CFP) for synchronizing drifting embedded clocks. To be specific, at the kth time synchronization cycle, upon the reception of a Sync packet (which is from node j and is transmitted at the time slot t k j ) after the packet-exchange delay κ ij [k], node i generates a timestampP i [k] via reading the counter register where κ ij [k] is the Gaussian random process with the mean of κ ij and the variance of σ 2 κ ij [11], [14]. Next, the utilization of the local timestampP i [k] can calculate the offset estimateθ i [k], following: In the meantime, the skew estimate is obtained fromγ Instead of employing the complete offset and skew estimates to a drifting clock, this article utilizes a static controller to improve synchronization performance, yielding where u θ i [k] and u γ i [k] are the offset and skew correction inputs, respectively. r θ i and r γ i are, respectively, the offset and skew reference inputs. α and β are the controller's parameters. Practically, due to limitations of the processor architecture, the processing delay η i [k] occurs, when the offset correction input u θ i [k] is applied to the counter register [8]. The clock's time variable actually is adjusted at the time where the processing delay η i [k] is the Gaussian random process with the mean ofη i and the variance of σ 2 η i . The extra value of processing delay is unintentionally employed to correct the local clock, and the effects of timestamping uncertainty are modeled in η i [k] [11]. This work compensates for the impacts of this processing delay via adding its mean value to u θ i [k], as shown in [8].
From (3), the employment of offset correction input u θ i [k] is equivalent to the clock correction action on θ i [k]. That is To correct the clock skew, the following expression is used: Remark 1: The packet-exchange delay κ ij [k] is almost deterministic, owing to the slot-based Sync packet transmission in CFP. The employment ofκ ij eliminates the effects of κ ij [k] [11]. Thus, in the experiments,θ i [k] of (9) is calculated from where t d ij = t d i − t d j is the difference of anti-phase synchronization duration between nodes i and j, and the anti-phase synchronization duration t d i is defined by , t dp means the contention access period, and the application data stream can be sent during this CAP. t sd represents the slot duration.
For the purpose of realizing collision-free packet transmission in CFP, r θ i and r γ i are, respectively, set to − t d ij and 0 to allocate the slot t d i for node i. Once a network system is at the steady synchronized state, the ith clock offset θ i [k] approaches t d i to realize the scheduling of wireless Sync packets, and γ i [k] converges to zero to achieve synchronization of drifting clocks. This Sync scheduling solution can help decrease the packet-exchange delay jitter, thereby improving synchronization precision.
Remark 2: Due to the difficulty of adjusting embedded clock frequency, in the experiments, the clock threshold correction is utilized as a substitute approach for the frequency adjustment, yielding where the threshold correction value

III. ROBUST OUTPUT FEEDBACK CONTROLLER
Apart from reducing packet-exchange delay jitter via the slot-based transmission mechanism, we also adopt the H ∞ control solution to let clock and delay noises possess a small impact on the accuracy, which further improves synchronization performance. This section starts by presenting the state-space representation of a static output feedback controller. Then, the H ∞ control is utilized to design the R-PkCOs parameters, thus guaranteeing the robustness of the proposed method in a spanning-tree clock synchronization network.

A. Output Feedback Controller in State Space
In contrast to the conventional continuous control system with delays, delays play a different role in the discrete time synchronization system. This means that the impacts of packet-exchange and processing delays of the synchronization system can be decoupled from the temporal dimension and are represented as biases or disturbances in the variable P i dimension [11]. The effects of packet-exchange delay in the temporal dimension can be removed by subtractingκ ij from the timestampP i [k] [8]. Thus, (7) and (8) are rewritten as where −κ ij is the offset measurement noise with the mean ofν θ i and the standard deviation of σ ν θ i .
] T , according to (15), the matrix-vector measurement equation is obtained where y i [k] is the clock output vector. ν i [k] is the measurement noise vector. C 2 is a 2 × 2 identity matrix. Likewise, (9) is also modified to the following form via defining the control vector u i where For the purposes of theoretical study, (11) and (12) are rewritten as T is the processing delay noise vector [11]. Through applying u i [k] to the ith embedded clock model (5), it is modified to where the disturbance vector consists of internal clock noises and external perturbations (from packet-exchange and processing delays). B is a 2 × 2 identity matrix. The matrix E is equal to E = 1 0 0 0 − 1 0 1 0 0 0 .
Eventually, the pairwise output feedback control synchronization system is given by where o i [k] is the performance output vector. The matrices C 1 , F, and H are, respectively, equal to As shown in (20), time synchronization is described as a state-space model, whose output is synchronization precision o i [k]. In addition, this model is also disturbed by clock and delay noises d i [k]. The purpose of the H ∞ control is to let d i [k] possess a tiny impact on the output accuracy o i [k]. In other words, by designing the static controller, the ratio between the modulus of the achieved synchronization precision and the magnitude of the noises is always less than a given value.

B. Controller Optimization
Here, we propose a design condition to guarantee that the networked system is robust in the presence of disturbances (i.e., d i [k]), caused by the drifting clock, and packet-exchange and processing delays. Mathematically speaking, Let r i be a 2 × 1 zero matrix, and the closed-loop system (20) is modified to the following form: where the matrices A, B, K, and C are, respectively, equal to Before carrying out the main work, we introduce the following preliminary lemma.
Lemma 1 [24]: For the square matrices X and S, and the matrices T = T T , A, P, L with appropriate dimensions, the following two inequalities are equivalent: Proof: (24), the inequality −SX T − XS T < 0 is obtained. This means that X is a nonsingular matrix. Through pre-and post-multiplying (24) with [I, A T X −1 ] and its transpose, we have Hence, (25) is obtained. (25) ⇒ (24): Let L = P, S = I, and X = κI, where the scalar κ > 0 , the matrix inequality (24) is modified to Based on the Schur complement, (27) is rewritten as Since T + (PA) + (PA) T < 0 holds, the sufficient large number κ > 0 guarantees that the above inequality (28) is true. Theorem 1: Given a spanning-tree clock synchronization network denoted by G, consisting of a perfect root node's clock and N sensor node clocks with nonidentical and drifting = f 0 and i ∈ N }, and a scalar ρ > 0. For the known parameters ζ and ξ = 0, if there exist the matrices Q > 0 ∈ R 2×2 and G ∈ R 3×3 , and the diagonal matrices V ∈ R 2×2 and U ∈ R 2×2 such that ⎡ Proof: The directed spanning-tree system G can be decomposed into N 2-D systems (22). For an arbitrary closedloop pairwise system, suppose that (29) holds, −(B T BU) − (B T BU) T < 0 implies that U is a nonsingular matrix. By defining U = ξ U, and letting the matrices T, L, A, P, S, and X in Lemma 1 equal to From (25) of Lemma 1, the following matrix inequality is obtained: Fig. 3. 50-node spanning-tree clock synchronization network.
Through defining K = U −1 V, according to (30), we have Based on [24] and [25], (31) is the bounded real lemma with the auxiliary variable matrix G. Once the matrix inequality (29) is established, the H ∞ performance ρ of any arbitrary pairwise system (22) is guaranteed. Since the spanning-tree network is a directed graph, the H ∞ performance of the networked system G is also guaranteed. This means that clock and delay noises in the spanning-tree clock synchronization network possess a small impact (i.e., ρ times) on the output accuracy.

IV. SIMULATION RESULTS
To validate the theoretical results in the preceding section, here, we conduct numerical simulations in a (randomly generated) 50-node spanning-tree network (see Fig. 3). For the simulations, the initial clock offset θ i [0] and initial skew γ i [0] are chosen randomly and uniformly in the corresponding intervals (0.4 s, 0.8 s) and (0 ppm, 50 ppm). The clock offset and skew are subject to random perturbations with the standard deviations σ θ i = 1 μs and σ γ i = 1 ppm, respectively. The synchronization cycle is 1 s. The standard deviation of packet-exchange delay is σ κ i = 4 μs [11]. This means that the standard deviations of offset and skew measurement noises [see (15)] are, respectively, 4 μs and around 6 μs.
The condition in Theorem 1 is used to design a static output feedback controller, the H ∞ performance ρ = 14.671 is obtained under ζ = 0.4895 and ξ = 0.4937. The control gain  In addition, two synchronization approaches, namely, PISync and TPSN, are also selected for performance comparison. Figs. 4 and 5, respectively, show the evolution of offset and skew over time. Clearly, all three solutions let both the clock offset and skew converge to corresponding constant values, and thus the steady synchronized state is achieved in the network. In the PISync and TPSN protocols, since the complete offset estimate is used for clock correction (i.e., α = 1), their convergence speed is faster than that of R-PkCOs (see Fig. 4). Even though the adaptive tuning method is utilized in PISync, the order of magnitude of β is still tiny and is less than 5 × 10 −07 (from the simulation results). Thus, such a small value of β cannot overcome the joint effects from the drifting clock frequency (with the standard deviation of 1 ppm) and ν γ i [k] (with the standard deviation of 6 μs). The failure of clock kew correction (see Fig. 5) also leads to worse precision of around 400 μs, as shown in Fig. 4. For the TPSN protocol, the drifting clock is adjusted by using the full clocks kew estimate (i.e., β = 1), which suffers from large clocks kew  As a result, an overcorrection occurs on γ i [k] (see Fig. 5), and the synchronization performance degrades. In R-PkCOs, the control gain K is obtained from Theorem 1, which implies that a small (i.e., less than ρ = 14.671 times) effect of clock and delay disturbances is on the output synchronization accuracy. Thus, the R-PkCOs protocol achieves better precision, compared to PISync and TPSN.
For PISync and TPSN, their corresponding under-and over-correction are also reflected in the evolution of Fig. 6). The proposed R-PkCOs method guarantees ℵ i of each node is smaller than 6. However, during the steady synchronized state, ℵ i of PISync and TPSN are only about 50 and 30, respectively.

V. EXPERIMENTAL EVALUATION
This section evaluates the performance of the proposed R-PkCOs synchronization method in a spanning-tree network (see Figs. 7 and 8). For the implementation, the clock's time variable is represented by a 32-bit counter register (i.e., COUNT) of the RTC module, which is driven by an external 32.768 MHz crystal oscillator. The threshold register (i.e., COMP) is set to 32767999 to let the embedded clock reset each second. Once COUNT matches COMP, the processor issues a hardware interrupt, where COUNT is reset to zero, read counter (P i [k] = counter); 10: estimate clock offset, according to (13); 11: adjust clock threshold, based on (14): 12: threshold = threshold + u ϕ i [k]; 13: correct counter, following: 14: if (P i [k] + u θ i [k] +η i ) < threshold then 15: counter =P i [k] + u θ i [k] +η i ; 16: elseif (P i [k] + u θ i [k] +η i ) ≥ threshold then 17: reset counter (counter = 0); 18: send_pkt(Sync); 19: end if 20: meanwhile, a 21-byte Sync packet is transmitted. Upon the reception of the wireless packet, the other hardware interrupt [i.e., address match interrupt (AMI)] is triggered to generate a timestamp, which is used for offset calculation and clock correction. In addition, Algorithm 1 presents the pseudocode of R-PkCOs.
During the experiments, the Trimble ThunderBolt E GPS Disciplined Clock [26] is connected to the root node, for providing the reference time [i.e., the pulse-per-second (PPS) signal] to the network (see Figs. 7 and 8). This means that the synchronization cycle T is one second. The average values of packet-exchange and processing delays are around 514. 25 and 117 μs, respectively, and the corresponding standard  deviations are of 0.3 and 0.3 μs. The control gains α and β are 1/1.3 and 1/8, respectively, which are the same as the parameters used in the simulations. t dp and t sd are set to 9.15 and 3.66 ms, respectively. The logic analyzer [27] is used to evaluate the performance, and the synchronization precision is defined as the time difference between the sensor node clock and root node's clock. Moreover, the PISync protocol is chosen for comparison. From Fig. 9, it can be seen that each sensor node possess a unique frequency drifting characteristic. The clock offset increments of 20 sensor nodes in the experiments are between −1.6 and 1.6 ms, if no time synchronization protocol is applied to the network. By using the proposed R-PkCOs protocol, the synchronization precision in the spanning-tree network is up to 6 μs; while, the first-hop node precision of PISync is about 20 μs, which also coincides with [21].
In addition, we also study the one-hour performance of the R-PkCOs protocol. The logic analyzer can only sample 100-s data; thus, the serial communication method [11] is utilized for data collection and analysis. Fig. 10(c) shows the time synchronization precision obtained by using the serial communication method. The precision converges from the initial value to around 6 μs, and this accuracy [from Fig. 10(c)] is similar to the performance calculated via the logic analyzer, as shown in Fig. 10(a) and (b). Overall, by using the slot-based one-way Sync packet transmission scheme and the control gain obtained from Theorem 1, R-PkCOs achieves time synchronization with the precision of about 6 μs during the one-hour experiments.

VI. CONCLUSION
In this article, we proposed the R-PkCOs protocol to correct both clock skew and offset for improving synchronization performance, subject to the impacts of drifting frequency, and external perturbations from packet-exchange and processing delays. The proposed algorithm not only uses the slot-based one-way Sync packet transmission mechanism but also adopts the H ∞ control method to guide the parameter selection, for letting clock and delay noises possess a tiny (i.e., ρ times) impact on the synchronization accuracy. Through designing the static controller, the ratio between the modulus of the achieved synchronization precision and the magnitude of clock and delay noises is always smaller than a given value ρ, thereby guaranteeing robustness of R-PkCOs. The one-hour experimental results show that the proposed protocol is capable of achieving clock synchronization with the precision of 6 ms in a 21-node spanning-tree network. Thus, the R-PkCOs synchronization technology can be applied in the IIoT applications to provide an accurate common sense of timing (up to 6 μs) among wireless nodes.